With the increasing interest in high-frequency and high-speed electronic systems, the rise time of a circuit system may get faster and the noise margin of the circuit system may deteriorate. Consequently, power integrity may become an issue. Skilled persons in the art will understand that it is important to maintain power integrity in a circuit system because signal integrity may not be achieved without a stable and low-noise power supply. Generally, the stability of a circuit system may largely depend on the noise immunity of the circuit. To provide a stable power supply, de-coupling capacitors may be used to suppress switching noise due to high-speed turn-on or turn-off in an integrated circuit (IC). A de-coupling capacitor may suppress glitches, attenuate noise and stabilize power supply. Furthermore, a de-coupling capacitor may be arranged near to a power or ground terminal of the IC so as to minimize parasitic inductance due to the length of a conductive path between the de-coupling capacitor and the IC. A lengthy path may adversely affect or impair the function of a de-coupling capacitor.
De-coupling capacitors may be mounted on a substrate, for example, a printed circuit board (PCB), an IC substrate, a flexible substrate or a silicon substrate, using known surface mount technology (SMT) and thus may be called “surface mount device” (SMD) capacitors. Alternatively, other types of capacitors may be mounted on or in the substrate and coupled with an IC to provide similar effects as those SMD capacitors. As the operation of ICs gets faster, the frequency of the associated noise, such as switching noise, also gets higher and more problematic, which may require more de-coupling capacitors and/or de-coupling capacitors with better characteristics. With the increasing speed of electrical circuits and the shrinking available substrate space, finding SMD capacitors that are capable of satisfying the design need becomes a challenge. Additionally, SMD capacitors mounted on a substrate requires certain substrate space and may limit the substrate space available for other devices. With the increasing terminals of IC and the densely arranged terminals, the wiring design for coupling the IC to external capacitors may also post another challenge.
Capacitors, which may refer to planar capacitors embedded or buried in a PCB, chip carrier or substrate, have been proposed to replace the SMD capacitors. As defined herein, a substrate may be comprised of an organic or inorganic material, including semiconductor, organic, ceramic, glass, flexible or metal materials. FIG. 1A is a schematic cross-sectional view of a conventional embedded capacitor device 10, and FIG. 1B is a schematic top view of the embedded capacitor device 10. Referring to FIG. 1A and also FIG. 1B, the embedded capacitor device 10 may include a first capacitor 11, a second capacitor 12 and a third capacitor 13. The first capacitor 11 may include a first electrode 111 coupled to a ground plane 14 through a first conductive via 11-1, and a second electrode 112 coupled to a power plane 15 through a second conductive via 11-2. Likewise, the second capacitor 12 may include a first electrode 121 coupled to the ground plane 14 through another first conductive via 12-1, and a second electrode 122 coupled to the power plane 15 through another second conductive via 12-2. Moreover, the third capacitor 13 may include a first electrode 131 coupled to the ground plane 14 through yet another first conductive via 13-1, and a second electrode 132 coupled to the power plane 15 through yet another second conductive via 13-2. The capacitors 11, 12 and 13 may individually serve as a de-coupling capacitor, but may not function as an intergraded unit to fast respond to switching noise, as will be explained below.
FIG. 1C is a diagram illustrating an impedance curve of the embedded capacitor device 10 illustrated in FIG. 1A. Referring to FIG. 1C, curves C11, C12 and C13 may respectively represent the impedance characteristics of the first, second and third capacitors 11, 12 and 13. The first capacitor 11 may be more suitable for processing high-frequency noise than the second and the third capacitors 12 and 13. On the other hand, the third capacitor 13 may be more suitable for processing low-frequency noise than the first and the second capacitors 11 and 12. Furthermore, the first, second and third capacitors 11, 12 and 13 may each include a capacitive region and an inductive region, depending on the operating frequency. As an example, the third capacitor 13 may exhibit more inductive than capacitive behavior when operated at a frequency higher than its resonance frequency fR. As a result, the impedance of the embedded capacitor device 10 may increase as the operating frequency increases, which may cause deterioration of its ability to suppressing switching noise. Moreover, referring back to FIG. 1B, high-frequency noise that may occur at, for example, the second electrode 122 of the second capacitor 12, rather than in time by the first capacitor 11, which is better suited for high-frequency processing than the second capacitor 12. Similarly, low-frequency noise that may occur at the second electrode 122 of the second capacitor 12 may not be processed in time by the third capacitor 13, which is better suited for low-frequency processing than the second capacitor 12. Consequently, the conventional embedded capacitor device 10 may not effectively respond to switching noise.